With the increasing functions of mobile phones and other portable handheld devices, the balance of design is becoming more and more fine. Popular functions such as text information and web browsing require more data input, which is difficult for the traditional dual tone multi frequency (DTMF) (0-9, #, *) keyboard. Using this keyboard requires multi terminal data input, which is inefficient and error prone.Figure 1 QWERTY keyboard (Motorola a630)One way to make text entry more convenient is to use the QWERTY keyboard (see Figure 1). This keyboard uses 40 or more keys, while DTMF phones usually use 12 keys. Of course, more keys will make the phone larger and use more electronic components.
However, text information users may be willing to trade volume for QWERTY keyboard, because text input is much easier, and both thumbs can be used to input text information or data. Recently, some mobile phone manufacturers have launched mobile phones with QWERTY keyboard for Text users.The data input keyboard can be designed in a variety of ways. Adding more keys to the traditional DTMF keyboard poses a challenge to designers. This paper discusses a possible solution to this challenge.QWERTY building block
Our solution uses Xilinx coolrunner - II CPLD "target ="_ Blank "> CPLD; low power consumption, small package and low cost make it an ideal choice for this application.Usually, the processor or DSP is used as an interface to connect keyboard rows and columns (see Figure 2). The processor scans rows and monitors columns to detect logical changes. When changes occur, it means that the user has pressed a key. Knowing which row is scanned and which column's state has changed, the processor can infer which key is pressed.Extended I / O
When designing a keyboard that requires more I / O (QWERTY keyboard is an example), it may be found that the existing processor does not have enough GPIO. One possible solution is to use a CPLD as an I / O extender to reduce the requirement for the number of processor I / O.Figure 3 uses a CPLD between the processor and the keyboard. One side is connected to the row / column of the keyboard and the other side is connected to the available GPIO of the processor. In this example, after using a CPLD, an 8 x 8 keyboard requires the same number of processor GPIO ports as a 4 x 4 keyboard (actually one less) . if CPLD is not used, the processor will need 16 GPIO ports instead of 7.Scanning and coding
In addition to reducing the number of gpios required by the processor, CPLD can also undertake some functions of the processor, such as scanning rows and monitoring columns to detect state changes. When the user presses a key, CPLD will stop scanning and immediately generate a codeword, and then send it to the processor to tell the processor which key is pressed. Because the codeword is used to inform the processor Which key is pressed to reduce the I / O demand on the processor.Figure 3 extending GPIO with coolrunner II CPLDIn the example shown in Figure 3, six bits are used to represent the codeword. The six bits provide 26 (i.e. 64) different values, and each value represents a key. However, there must also be a value representing the state that no key is on time. Therefore, in this example, only 63 keys can be represented without adding another GPIO.
The processor does not need to scan the keyboard because this operation is now performed by the CPLD; however, the processor still needs to monitor changes on its GPIO - it just doesn't need to infer which key is pressed because the information is encoded in a six bit word.Switching jitter is also needed, which can be arranged in CPLD or processor, depending on which device has available resources. This operation in processor can minimize the size and cost of CPLD.This design example is briefly summarized: CPLD scans the keyboard, detects the pressed keys, and then provides a coded word for the processor to read and analyze. This function not only eliminates the scanning task of the processor, but also expands the function of GPIO.
This design is very suitable for coolrunner II 32 macro unit device (utilization rate is about 75%), leaving 25% space for other purposes. In addition, this design also adopts other methods to reduce power consumption and take advantage of the energy-saving function of coolrunner II.CPLD design detailsTo scan the rows of the keyboard, all bits of the barrel shift register are preset to 1 except one bit is preset to zero. Each bit of the shift register drives an output pin on the CPLD, which is connected to the row of the keyboard. When the shift register starts timing, the zero bit is shifted through the barrel shifter, and the row is set low row by row to scan it. The column of the keyboard is input to the CPLD, and each Each input is pulled up through an internal pull-up resistor.
When no key is pressed on time, all column inputs of CPLD are passively pulled up to the logic high level. The "and" operation is performed for all column inputs together. At this time, the logic 1 at the output end indicates that no key is pressed.The output of the and operation is used to start the shift register. When the key is pressed, the column is connected to the row, and the column in which the key is pressed is set low by the row related to the key. The output of the and operation will become zero, which stops the shift register when the key is pressed.At this time, the shift register sets the row of the pressed key low and the column of the key low. In order to correlate these information, two encoders are used: one for row bits (output of the shift register) The other is used for column input. The outputs of the two encoders are combined to form the codeword sent to the processor. Fig. 4 is a block diagram of this operation.
ConclusionUsing Xilinx coolrunner II CPLD, you can obtain flexible design and low power consumption. In addition to I / O expansion, CPLD can also add other "bonding" functions, such as voltage conversion, I / O standard conversion and input lag.Because CPLD is programmable, you can use the same device for different keyboards and products with the effect of high output and low cost. The reprogrammable feature is supplemented by simple and easy-to-use design tools, so that you can make late changes to the design and reduce risks.