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# Design of 16 Order Linear Phase FIR Digital Low Pass Filter Based on FPGA Using Window Function Meth

With the development of microelectronics technology, digital signal processing using field programmable gate array FPGA has developed rapidly. Because FPGA has the characteristics of field programmable and can realize ASIC, it is more and more favored by hardware circuit design engineers. This paper studies the implementation method of FIR digital low-pass filter hardware circuit based on FPGA. The internal circuit structure of the filter is transparent, the volume is reduced and the working efficiency is improved.

The method of designing linear phase FIR filter by window function method

Frequency response H (EJ) of any digital filter All Its Fourier series expansion is:

Fourier coefficient h (n) is actually the impulse response of digital filter. One possible way to obtain finite impulse response digital filter is to intercept the infinite series of equation (1) into finite series to approximate it, and the well-known Gibbs phenomenon makes the direct interception method unsatisfactory.

The window function method uses the finite weighted sequence w (n) called window function to modify the Fourier coefficient of formal (2) to obtain the required finite impulse response sequence HD (n), namely:

W (n) is a finite length sequence. When n > n-1 and N Here, we only take the low-pass filter when the impulse response is symmetrical, that is, H (n) = H (n-1-n) (n = 0, 1, 2,..., n-1) as an example. The frequency response function H (EJ) of the low-pass filter As shown in equation (4).

Among them, Is the frequency normalized to the sampling frequency, C is the normalized cut-off frequency.

The impulse response H (n) corresponding to equation (4) is obtained by using the inverse Fourier transform formula, as shown in equation (5).

Hanning window is selected as the window function, and the function is shown in equation (6).

2 hardware circuit design of sixteenth order FIR low-pass digital filter

The following takes a sixteenth order FIR low-pass filter as an example to illustrate the design method and process of hardware circuit.

Cut off frequency: 37.5khz

Type: low pass input data width: 8 bits

Order: 16 order output data width: 16 bits

2.1.2 parameter extraction

The frequency response function and Hanning window function of the low-pass filter introduced above are used for design. The calculated characteristic parameters of the linear phase 16th order FIR digital low-pass filter meeting the design index are as follows:

2.2 unit circuit design

FIR low-pass digital filter circuit is divided into data bit expansion, parallel serial converter, shift register bank, pre addition unit, intermediate processing unit, post-processing unit and control unit. Its composition block diagram is shown in Figure 1.

2.2.1 data bit extension

The input of FIR digital filter designed here is 8 bits wide. In order to prevent overflow and ensure the normal operation of the circuit, the symbol bit expansion method is adopted. After symbol bit expansion, the total input data width is 9 bits.

2.2.2 parallel / serial converter

The parallel / serial converter is composed of 9 2-out-of-1 selectors and 9 d flip flops. Its structure is very simple. Its circuit structure will not be described here. Its working process is: the parallel / serial converter periodically collects 8-bit sample data at the sampling rate and outputs 1-bit data stream to the shift register of the later stage.

2.2.3 shift register group

The register group mainly completes the shift function.

The main function of the preamble unit is to pre add the 1-bit serial data stream output by the shift register. It is composed of a 1-bit serial adder. XC4000 series chips have the following two characteristics:

(1) Internal basic unit CLB (configurable logic module) It includes three function generators marked with F, G and h respectively. Each of the two first level function generators F and G can realize any function with 4 inputs. At the same time, they can also be combined with the H function generator to generate any function with 5 inputs. In addition, CLB also has the feature that the delay of CLB internal connection is less than that of external connection.

(2) XC4000 series provides CArray logic to accelerate the carry channel of adders and counters. Using fast carry logic, adders and counters, it has extremely fast working speed when occupying the minimum number of CLBs. Moreover, the carry logic can be flexibly configured to realize counters and subtracters of any length.

Therefore, from the aspects of improving chip utilization, wiring rate and reducing circuit delay, we must make full use of the characteristics of XC4000 series chips to make a special design for the 1-bit full adder in the circuit suitable for the characteristics of FPGA. The circuit in Figure 2 is the optimized 1-bit full adder circuit including fast carry logic adopted in this paper, in which fmap is function mapping, and specific circuits can be mapped To F, g or H function generator of CLB; CY4 is fast carry logic macro unit.

2.2.5 intermediate processing unit

In FIR digital filter, the intermediate processing unit mainly realizes the functions of multiplication and accumulation of 1-bit serial output data from the pre adding unit. Here, the distributed algorithm based on ROM look-up table method is used to design the circuit of the intermediate processing unit.

As mentioned earlier, this paper only considers the case that the impulse response is symmetrical, that is, the coefficients of the filter are symmetrical, so the number of independent coefficients should be equal to the order of 1 / 2. For the FIR filter of order 16, the number of independent coefficients is 8. These 8 independent coefficients are stored in 2 ROM based look-up tables according to the combinations shown in Table 1.

2.2.6 post processing unit

The main function of the post-processing unit is to round the data and get the required data from the data stream. A 16 bit adder is required to complete the rounding function, and a 16 bit parallel D trigger is required to get the data.

2.2.7 control unit

The control unit is mainly composed of counter and D flip-flop. Its control of the circuit mainly includes: global reset before the circuit starts to work, making work preparations; controlling the work of the input unit; providing some signals necessary for the normal work of the intermediate processing unit; and providing the output synchronization signal (outsyn) when the final output result is provided.

2.3 circuit principle and function simulation

The hardware circuit of the 16th order FIR low-pass digital filter designed by xc4005epc84 of Xilinx company is adopted, and the circuit schematic diagram of the top layer is shown in Figure 3.

Figure 3 is the upper layer diagram of FIR digital filter. See Table 2 and table 3 for input and output pins and hardware resource occupation respectively.

In order to check whether the designed circuit can work continuously and correctly, 16 bit data (decimal system) are continuously input, which are 100101102103104105106107, - 101, - 102, - 103, - 104, - 105, - 106, - 107. Hardware simulation results of FIR digital filter (the first 16 outputs) As shown in Table 4, the software calculation results obtained by the program written according to literature  are also listed in Table 4.

From the above data, it can be seen that compared with the hardware simulation results, the absolute value of the error is 1, so it can be considered that the hardware circuit of the filter works correctly.

In addition, in order to verify whether the filter can work correctly when the edge value is input, the edge value test is also carried out. When the input data is 8 bits, the two edge values are 127 and - 128 respectively, corresponding to hexadecimal 7F and 80. Using these two groups of data as input, the output is also compared with the software results, which can prove that the circuit can also work correctly at this time.

When the 16th order linear phase FIR digital low-pass filter designed in this paper is realized by xc4005epc84-2 chip, the system clock frequency of data processing is 36MHz, the sampling rate is 4MHz, and the maximum error between the calculation result and the software calculation result is 1. In practical use, the FIR filter can be easily modified according to different accuracy requirements to meet different index requirements In addition, based on the low-pass filter designed in this paper, the high pass or band-pass filter can be obtained by simply reorganizing the filter characteristic parameters. At the same time, the programmable characteristics of FPGA device can easily improve the circuit and further improve the circuit performance.

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